1. Field of the Invention
The present invention relates to a deformable mirror device (DMD), and more specifically, the present invention relates to a method of driving a DMD.
2. Description of the Related Art
The development of high intensity, high definition flat panel displays (FPDs) has been advancing in recent years. Displays such as liquid crystal displays, EL (electroluminescence) displays, and plasma displays can be given as examples of FPDs.
Furthermore, in addition to the above FPDs, digital micromirror devices (hereafter referred to as DMDs) have been in the spotlight. Techniques related to DMDs have been disclosed by Texas Instruments, Inc., in patent applications such as: Japanese Patent Application Laid-open No. Hei 5-150173, Japanese Patent Application Laid-open No. Hei 5-183851, Japanese Patent Application Laid-open No. Hei 7-240891, Japanese Patent Application Laid-open No. Hei 8-334709, Japanese Patent Application Laid-open No. Hei 8-227044, Japanese Patent Application Laid-open No. Hei 8-051586, and Japanese Patent Application Laid-open No. Hei 8-227044.
A plurality of micromirrors approximately 16 μm×16 μm in size are formed having a pitch of 17 mμ on a CMOS SRAM formed on a silicon substrate, and each of the micromirrors corresponds to a screen pixel, in the DMD. The number of micromirrors reaches 480,000 for SVGA, 786,000 for XGA, and 1,300,000 for SXGA.
The angle of the micromirror changes by an angle θ with respect to the substrate if a digital signal having image information (digital video signal) is input to the SRAM of the DMD, in accordance with an electric field effect due to voltage from the SRAM. If the angle of the micromirror with respect to the substrate changes by an amount θ (where 0<θ<90°), then light from a light source is separated into two directions when reflected in the micromirror. One of the lights separated into two directions is absorbed by a light absorber, while the other arrives at a screen and forms an image.
Note that the term digital signal denotes a signal having two voltage values in this specification. Of the two voltage values, the higher is indicated by the term HI, while the lower is indicated by the term LO.
Schematic diagrams of a structure of a general DMD pixel are shown in FIGS. 20A and 20B. FIG. 20A is a perspective diagram of a DMD pixel, and FIG. 20B is a cross sectional diagram of the DMD pixel of FIG. 20A. A plurality of pixels are formed on a substrate 901, and each pixel has a first electrode (first address electrode) 902a, a second electrode (second address electrode) 902b, landing sites 903, a micromirror 904, a hinge 905, and hinge support posts 906.
The angle of the micromirror 904 with respect to the substrate 901 is changed by an amount θ with the hinge 905 acting as a rotational axis. The hinge 905 is fixed on the substrate 901 by the hinge posts 906.
A portion of the micromirror 904 contacts the landing site 903 when the micromirror 904 is inclined to an angle greater than θ with respect to the substrate with the hinge 905 as an axis of rotation. The landing site 903 is maintained at the same electric potential as that of the mirror 904, or has insulating properties.
The electric potential of a digital video signal input to the pixel is imparted to the first address electrode 902a. Further, the digital video signal is inverted with electric potential of ground as a standard point, and the inverted signal is imparted to the second address electrode 902b as an inverted digital video signal.
A fixed electric potential (standard electric potential) is imparted to the micromirror 904. The micromirror 904 is then inclined by an angle θ to the first address electrode 902a side if the electric potential difference between the standard electric potential and that of the digital video signal is greater than the size of the electric potential difference between the standard electric potential and that of the inverted digital video signal. Conversely, if the electric potential difference between the standard electric potential and that of the digital video signal is smaller than the size of the electric potential difference between the standard electric potential and that of the inverted digital video signal, then the micromirror 904 is inclined by an angle θ to the second address electrode 902b side.
Digital light processing (DLP) with a projector using a DMD having the above structure differs from a projector using liquid crystals, and there is no light loss from a polarizing plate, and the aperture ratio is equal to or greater than 90%; the efficiency of utilizing light is therefore high. Further, this is a reflective type device, differing from general transmission type liquid crystal panels, and therefore the spacing between pixels, namely the spacing between the micromirrors, is small at about 0.8 μm, and a high definition image can easily be obtained even a projection is enlarged on the screen. In addition, no thermal problem develops like that of liquid crystal panels using thin film transistors because DMDs have superior cooling efficiency, and it is possible to use a high power light source, and therefore making projectors high definition becomes easy.
A drive circuit of a pixel in a conventional DMD is shown next in FIG. 21. Reference numeral 911 denotes a data driver, reference numeral 912 denotes a scanning driver, and reference numeral 914 denotes a pixel portion. The pixel portion 914 has a plurality of pixels 913.
The digital driver 911 inputs a digital video signal into a plurality of data lines 918, and the scanning driver 912 inputs a scanning signal into a plurality of scanning lines 917. Regions having one data line 918 and one scanning line 917 correspond to the pixels 913 for the case of the DMD shown by FIG. 21.
The pixels 913 each have a switching transistor 915, and a SRAM 916 having a plurality of transistors. A gate electrode of the switching transistor 915 is connected to the scanning line 917. Further, one of a source region and a drain region of the switching transistor 915 is connected to the data line 918, and the other is connected to an input terminal Vin of the SRAM 916 and to the first address electrode 902a. 
Note that the term SRAM denotes a static RAM having no transfer gates throughout this specification. If HI input is imparted to the SRAM, then LO output is obtained, and if LO input is imparted to the SRAM, then HI output is obtained.
Conversely, if a HI output is imparted to the SRAM, then a LO input is obtained, and if a LO output is imparted to the SRAM, then a HI input is obtained.
Note that, throughout this specification, the term transistor denotes an electric field effect transistor, which functions as a switching element.
An output terminal Vout of the SRAM 916 is connected to the second address electrode 902b. Further, Vddh denotes a high voltage side electric power source, and Vss denotes a low voltage side electric power source.
The switching transistor 915 is selected in the DMD shown in FIG. 21 by the scanning signal input to the scanning line 917 from the scanning driver 912. Note that, in this specification, the term selection of a wiring denotes a state in which all transistors whose gate electrode is connected to the wiring are on.
The digital video signal is then input to the data line 918 from the data driver 911. The input digital video signal is input to the input terminal Vin of the SRAM 916, and to the first address electrode 902a, through the switching transistor 915 in an ON state. The digital video signal input to the input terminal Vin of the SRAM 916 is inverted, with the ground electric potential as a standard, and is then output from the output terminal Vout as an inverted digital video signal, and input to the second address electrode 902b. 
If the digital video signal and the inverted digital video signal are input to the first address electrode 902a and to the second address electrode 902b, respectively, then the angle of the micromirror 904 of the pixel with respect to the substrate is selected in accordance with the 1″ or 0″ information of the digital video signal. Whether light from a light source is irradiated to a screen, or is irradiated to a light absorber, is selected when the angle with respect to the substrate is selected.
The digital video signal is then input in order to all of the pixels 913 of the pixel portion 914, and the micromirror angles are selected. Note that, in this specification, the term digital video signal input to the pixels 913 refers to the digital video signal being input to the source region or the drain region of the switching transistors 915 of the pixels 913.
If the digital video signal is then once again input to the same pixels, the micromirror angles are selected again.
Time division gray scale display of a conventional DMD is explained next using FIG. 22. The horizontal axis shows a time scale, and the vertical axis shows the position of a scanning line in FIG. 22.
A plurality of subframe periods are formed in one frame period with the time division gray scale display used by conventional DMDs.
An example in which n subframe periods are formed within one frame period is shown in FIG. 22. By then selecting the angle of the micromirror in each of the n subframe periods in accordance with the digital video signal, light from the light source is irradiated to the screen or to the light absorber. Hereafter, light irradiated to the screen is referred to as white display, and light irradiated to the light absorber is referred to as black display.
White display or black display is selected from the first subframe to the number n subframe in accordance with the first bit to the number n bit of the digital video signal.
By selecting white display or black display in the n subframe periods, the length of the white display periods and the length of the black display periods within one frame period can be controlled. As a result, the gray scale of an image formed by one frame period can be controlled.
However, if the number of gray scales of the image displayed is increased with the conventional DMD time division gray scale display shown in FIG. 22, the length of the subframe periods becomes shorter. A problem therefore develops in that the write in speed of the digital video signal to the pixels cannot be managed. This problem is explained in detail below using FIG. 23.
The horizontal axis of FIG. 23 shows a time scale, and the vertical axis shows the position of a scanning line. Further, reference symbol t1 denotes the length of a period for writing in the number i bit of the digital video signal to the pixel, and reference symbol t2 denotes the length of a subframe period SFi.
For the case of the drive shown in FIG. 23, t1≦t2, and the number i bit of the digital video signal is written into all of the pixels before the number i subframe period SFi is complete and the number (i+1) subframe period SF(i+1) begins. Write in of the number i bit of the digital video signal to the pixels and write in of the number (i+1) bit of the digital video signal to the pixels are therefore not performed in parallel within the same pixel portion.
However, if the number of gray scales becomes larger, and the number i subframe period SFi becomes shorter, then t1>t2. In this case, there are times when write in of the number i bit of the digital video signal to the pixels is not complete, even though the number i subframe period SFi is finished. In other words, write in of the number (i+1) bit of the digital video signal to the pixels must be performed in parallel with write in of the number i bit of the digital video signal. With the DMD structure shown by FIG. 21, drive in which t1>t2 is impossible.